Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...

Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, ...

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant Challenges facing chip design verification engineers are ...

Evolving Verification Environments It was standard practice in the early days of hardware design to design a chip and then verify it. However this methodology started to break down in the 1980s when ...

The limitations of traditional SPICE simulations. Role of production-grade AI in transforming EDA. Applications of AI in day-to-day engineering. The future of AI in analog design. In the realm of ...

Discover how this powerful open-source SPICE simulator helps you analyse and validate analog, digital and mixed-signal ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

In partnership with the Israel Tech Challenge, Apple is co-hosting an event at its Israel headquarters to discuss a new Design Verification Engineering course. This course will be a ten month-long ...

Acquisition integrates advanced "shift-left" Design for Test (DFT) functionality into Siemens' Xpedition and Valor portfolios ...